1. Field of the Invention
The present invention relates to memories, and particularly to non-volatile memories such as EEPROM (Electrically Erasable Programmable Read Only Memory) or Flash memories.
The present invention applies more particularly to memories accessible by a serial bus such as an SPI (Serial Peripheral Interface) or an I2C bus.
2. Description of the Related Art
One example of a memory accessible by a serial bus is represented in FIG. 1. The memory MEM represented in FIG. 1 comprises a memory array MA, a control device CTL, a booster circuit HVCT, an address register ADR, a data register DTB, an input/output register IOSR, a status register STR, a line decoder RDEC and a column decoder CDEC.
The control device CTL receives from the external environment a selection signal CS for selecting the memory MEM and a clock signal CK. The device CTL controls the register IOSR and the status register STR, and supplies a control signal VC for controlling the circuit HVCT. The circuit HVCT supplies a high voltage Vpp required to program and erase memory cells of the memory array MA. The register IOSR receives commands and exchanges data with the external environment of the memory through a serial bus DB. The register IOSR is paced by the clock signal CK and receives the commands, data and addresses transmitted by the bus. In write mode, the register ADR receives from the external environment through the serial bus DB and the register IOSR an address of memory cells to be read, programmed or erased, and the register DTB receives data to be stored in the memory array MA. The status register contains information concerning the status of the memory MEM. The address contained in the register ADR is used to control the decoders RDEC and CDEC that enable memory cells to be programmed, to be erased or to be read to be selected according to the address supplied by the address register.
The memory is accessible through read and write commands. The commands applied to the memory are decoded using a finite state machine integrated into the control device CTL.
An example of a control device CTL is represented in FIG. 2. In FIG. 2, the control device CTL comprises a clock signal input CK, a main state machine MFSM, a write state machine WFSM and a detector circuit PRDT for detecting the switching on of the memory MEM and generating an initialization signal POR when the memory is switched on.
The state machine MFSM particularly decodes the commands applied to the memory, and activates the write state machine WFSM when the command received is a write command. The state machine WFSM supplies the signal VC that particularly drives the booster circuit HVCT during the phases of writing the memory. The circuit PRDT activates the signal POR following the switching on of the memory (when the supply voltage exceeds a certain threshold value). The state machine MFSM receives the selection signal CS for selecting the memory MEM, and the serial control signal DT transmitted by the bus DB for accessing the memory. The state machine MFSM also receives, through an OR-type logic gate OG1, the initialization signal POR and another initialization signal RST. The signal RST comprises one pulse upon each falling edge of the signal CS. The state machine MFSM supplies the state machine WFSM with a start-write signal SP upon the execution of a write command.
The state machine WFSM is also initialized by the signal POR and supplies the state machine MFSM with a busy signal RB indicating when a write phase is in progress. The signal RB is applied to an activation input En of the state machine MFSM. When the signal RB is active, the state machine MFSM is blocked, but can nonetheless receive and process a command applied to the memory.
The state machines MFSM and WFSM are generally produced using programmable logic arrays PLA. The state machines are initialized using the signal POR when the memory MEM is switched on. In addition, the programmable logic array of the state machine MFSM is initialized by the signal RST at the start of each access to the memory so as to always start in a same well-defined state. The logic circuit around the state machines must also be initialized in a same well-defined state to operate properly.
However, due to certain protocol requirements in particular, certain parts of the device CTL cannot be initialized at the start of the receipt of a command. Thus, the initialization signal RST cannot be applied to the state machine WFSM given that the write commands in the memory are executed following the deselection of the memory (rising back up of the signal CS).
If, for any reason (disturbance on the supply voltage, an electrostatic discharge, failure of the memory cells, etc.), the device CTL is put into an inhibited state, the memory can no longer operate correctly and the reliability of the subsequent accesses to the memory is affected.
In particular, when the memory is write-controlled, the state machine WFSM sends the busy signal RB that blocks the main state machine MFSM while the writing operation is in progress. While the busy signal RB is active, the initialization of the control device CTL, which is normally performed upon each new access to the memory, is not executed following a change of state of the signal CS (the signal RST is not generated). If an operation of writing in the memory has not taken place correctly, the busy signal RB can remain active. Then the result is that the memory is blocked. The only way to restore the memory to a normal state is to temporarily cut off the power supply of the memory. In applications such as motor cars, it is not acceptable to have to cut off the power supply to reset the circuits. Even if the memory is no longer functional, it must still be able to execute read commands.
Thus, it is desirable to reduce the risks of improper operation of the control device of a memory by providing for performing an initialization of the control device which is as complete as that obtained by switching off the circuit.